As a semiconductor device including a scanning mechanism in order to facilitate a manufacturing test or an evaluation, a large scale integrated circuit (LSI) or the like is known. As a mechanism of detecting an internal state of the LSI, a scan chain is included in the scanning mechanism. The scan chain has a structure in which a plurality of memory circuits (scan flip-flops or latch circuits) are coupled in series between an external input terminal and an external output terminal of the semiconductor. For the scan chain, an LSI tester may control the internal state of the semiconductor by inputting a signal from the external input terminal of the semiconductor, and observe the internal state by detecting a signal output from the external output terminal so that a test may be easily performed.
Meanwhile, in order to verify whether the scan chain is correctly coupled in a design stage, a simulation may be executed on a computer in a design verification process of the semiconductor. At the time of simulation, at each cycle of a clock signal, for example, a test pattern in which 0 and 1 are repeated a predetermined number of times, and all other values are 0's or 1's is input to the scan chain from the external input terminal of the semiconductor. Then, it is checked whether a value output from the external output terminal is equal to an expected value input to the external input terminal after each memory circuit of the scan chain performs a shift operation in synchronization with the clock signal a predetermined number of times.
As the circuit scale of a semiconductor has recently increased, the number of memory circuits included in a scan chain also increases.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication Nos. 2003-194886, 2006-004509, and 2012-146865.